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iris bahar

Department Head and Professor, Computer Science
Department of Computer Science


Since January 2022, Iris Bahar is the Computer Science Department Head and Professor at the Colorado School of Mines. Her research interests lie broadly in areas of computer system design and design automation. A main theme of her research over the years has been energy-efficient and reliable computing, from robots, to high-end processors, embedded systems, and emerging technologies.

Between her M.S. and Ph.D. studies, she worked for 5 years at Digital Equipment Corporation, mainly on their VAX microprocessor designs. Prior to joining CS@Mines as Department Head, she was faculty at Brown University for 26 years with a joint appointment in the School of Engineering and Department of Computer Science. 

Her research has been continuously funded since 1997 through various industrial and government sources, including the NSF (including a career award), DARPA, DoD, the Semiconductor Research Corporation (SRC), Intel, IBM, Facebook, and NASA. She is the 2019 recipient of the Marie R. Pistilli Women in Engineering Achievement Award and the Brown University School of Engineering Award for Excellence in Teaching in Engineering. She is an IEEE Fellow and ACM Distinguished Scientist.    



  • BS in Computer Engineering, University of Illinois, Urbana 1986
  • MS in Electrical Engineering, University of Illinois, Urbana 1987
  • PhD in Electrical and Computer Engineering, University of Colorado, Boulder 1995


Prof. Bahar has published over 200 articles on diverse topics in electronic design automation, computer architecture design, and low power computing. While much of her work falls within “classical” computer systems themes, she is also interested in working in interdisciplinary areas that bring together researchers from across the engineering disciplines and beyond. Most recently, her research interests have evolved to include approximate computing, robotics, machine learning, and security. 

Research Projects

Concurrent Near-Data Processing Architectures
Recent advances in memory architectures have provoked renewed interest in near-data-processing (NDP) as a way to alleviate the “memory wall” problem. An NDP architecture places logic circuits, such as simple processors, in close proximity to memory. This is distinct from processing-in-memory (PIM) where logic computation is effectively integrated into the memory cells/arrays. More ->

Robust and Computationally-Efficient Scene Perception 
Technological advancements have led to a proliferation of robots using machine learning systems to assist humans in a wide range of tasks. However, we are still far from accurate, reliable, and resource-efficient operations of these systems. More ->

Modeling of Fundamental Noise Effects in Nanoscale Circuits 
Near-threshold and sub-threshold voltage designs have been identified as possible solutions to overcome the limitations introduced by energy consumption in modern VLSI circuits. However, aggressive voltage and gate length scaling will reduce the reliability of logic circuits due to the increasing impact of noise and variability effects. More ->

Managing Microarchitecture Timing Violations with Hardware Transactional Memory 
Scaling of semiconductor devices has enabled higher levels of integration and performance improvements at the price of making devices more susceptible to the effects of static and dynamic variability. Adding safety margins (guardbands) on the operating frequency or supply voltage prevents timing errors but has a negative impact on performance and energy consumption. More ->


1650 Arapahoe Street
Colorado School of Mines
Golden, CO 80401